FIG. 1 shows a conventional 2×2 array 10 of imaging pixels 12. As illustrated, each imaging pixel 12 includes a photosensitive element 14 and a readout element 15. FIG. 1 shows an active pixel design in which the readout element includes four transistors, namely, a transfer gate 16, a reset transistor 18, a row select transistor 20, and an amplifier transistor 22. More or less transistors could be incorporated into the readout element, as is well known in the art. The photosensitive element 14 of FIG. 1 is a p-n junction photodiode, although it could be any number of photosensitive elements, including, but not limited to MIS photosensors, p-i-n photodiodes, and the like. The transistors are thin-film transistors (TFTs).
As generally known, when light strikes the array, electron-hole pairs are created. The holes diffuse through the p-type substrate to the contact on the back of the wafer. The electrons are held on the photodiode capacitance, and are selectively readout through the transfer gate 16, the amplifier transistor 22, and the row select transistor 20. Following readout, the reset transistor 18 is turned on, resetting the photodiode bias to its original value.
Imaging arrays such as those just described can be fabricated in any number of known ways. FIG. 2 illustrates a cross-section of a pixel fabricated from single crystal silicon wafers. More particularly, FIG. 2 shows a cross section taken through the photodiode 14, transfer gate 16, and amplifier transistor 22 of FIG. 1. In FIG. 2, a p-doped single crystal silicon wafer 30 is disposed on a metal contact 32. The p-n junction photodiode is formed by the p-doped substrate (p-side) and a diffusion or ion implant of phosphorous or arsenic n-type dopant (n-side) 34.
Another known imaging array uses thin-film transistors on glass. FIG. 3 illustrates a cross-section of a device in which the pixel 12 is formed in this manner. The photosensitive element 14 is an MIS photosensor and the readout element 15 is a single TFT. More transistors also could be included. In fabrication, a first level of metal 42 is deposited on a glass substrate 40. The metal 42 forms both the transistor gate for the readout element 15 and the back contact for the photosensitive element 14. A gate dielectric 44 is disposed on the metal layer 42 to form both the transistor gate dielectric and the gate dielectric for the photosensor. An undoped layer 46 thereafter is formed on the dielectric 44 to form the semiconductor layer for both the photosensitive element and the TFT. Heavily doped n-type amorphous silicon 48 forms the source and drain regions of the TFTs and the n-side contact to the MIS photosensor. Another layer of the gate dielectric thereafter preferably is disposed over the n-type amorphous silicon 48, and metal layer 50 forms the source and drain contact metallization and the vertical interconnect for the array.
In the prior art arrays just described, as in other known arrays, a silicon layer forms the semiconductor for both the photosensitive elements and the readout elements. This is a relatively low-cost fabrication method, because it minimizes fabrication steps. However, for most applications the desired thickness of the layer for imaging functions is much larger than the thickness desired for TFTs. That is, an increased thickness is desirable to absorb light, and that thickness preferably is one or more optical absorption depths. A preferred thickness typically is on the order of about one to two microns. However, thin-film-transistors fabricated from semiconductor layers that are relatively thick display significantly higher leakage currents in the off state. A preferable silicon thickness for TFTs is usually on the order of about 30-60 nm.
Differing the thickness of silicon for the imaging sensor and the TFT has been achieved in some conventional pixel designs by stacking the photosensitive element on top of the TFT. That is, the TFT first is formed on a substrate and once completed, or substantially completed, the photosensitive element is formed by subsequently formed layers. An illustration of a conventional pixel of this type is illustrated in FIG. 4. As shown, the readout element 15 is disposed beneath the photosensitive element 14.
While the vertical pixel structure of FIG. 4 allows for greater control of the thicknesses of the semiconductor layers for the photosensitive and readout elements, fabrication includes numerous steps and is therefore more expensive.
Thus, there is a need in the art for an improved manufacturing method that allows for different thicknesses of semiconductor layers in a planar imaging array. There also is a need in the art for an imaging array having semiconductor layers of different thicknesses.